The present invention relates to systems for code-delivery management capable of handling demand-paging code, independent of a host-system processor and operating system, and without latency.
Memory-management systems are well-known in the art of computer engineering as means for enhancing the performance of fast, random-access memory (RAM) by dynamically swapping sub-areas of RAM with other larger (but slower) storage memory, so that the fast RAM can always be available for use in program execution. Such systems are controlled by a memory-management unit (MMW).
In the prior art, a typical memory-management system includes a host processor (having an internal or external MMU), non-volatile memory (NVM, which is a large, but slow, memory), and RAM (which is typically fast, small volatile memory (VM) for code execution).
The MMU typically maps areas in the RAM to the NVM. The host-system processor loads code in the following ways:                (a) upon application request, when one application intentionally attempts to load and run another application that happens to be stored in the NVM (e.g. the dynamic-link library, or DLL, in MS Windows™);        (b) upon page fault, when an unintentional “page fault” situation occurs, the MMU is responsible for loading the data from the NVM, and does so using the following sequence of operations:                    (i) code caching: when possible, the MMU keeps the active code in a cache memory, eliminating the need for the host-system processor to read the code from an external resource (e.g. DRAM/RAM or any external storage device); this reduces the number of transactions (reducing power consumption), and improves processor performance and throughput;            (ii) mapping virtual addresses to physical addresses, using virtual-to-physical conversion tables enables software programs to implement a mechanism for demand paging, as explained below, and typically used by various operating systems (e.g. Windows Mobile, Symbian, and Linux);            (iii) a demand-paging mechanism is one of several implementations (enabled by the MMU) that makes the virtual-memory space equivalent to, or larger than, the physical-memory space;                            (A) When a demand-paging mechanism is activated, and the host-system processor tries to read content (e.g., during code execution or data used by code) from the virtual-memory space, the MMU calculates the requested virtual page, and looks for the page in the internal cache;                (B) If the page is not in the cache, the MMU looks in the virtual-to-physical table for the physical address in the RAM where the code or data is located;                (C) If the code or data is not mapped to a RAM physical address (and therefore cannot be retrieved), then a page fault occurs; and                (D) In response to the page fault, the MMU invokes an exception-interrupt to the host-system processor, which is expected to provide the missing page from the NVM.                                                
The main problem with the prior-art approach described above is the complexity of the process. Such a process becomes difficult to handle due to the plurality of management systems, drivers, and protocols that are involved. In the prior art, Microsoft Windows CE (4.2 and higher versions) supports demand paging. To support the demand-paging mechanism, a developer needs to provide specialized integration for the operating system. During development, the developer needs to install a file-system driver and a block device driver, and format the storage memory in a unique way (i.e. not similar to any integration required for storage memory that does not store code for demand paging).
A memory-management system in which the host-system processor requests data from one location, and always gets the data from that location (either directly or indirectly), is needed. However, the host-system processor demands to get the data synchronously, and within a very short response time (e.g. typically 4-5 clock cycles). Since some of the system components (e.g. the NVM) cannot work synchronously and/or are unable to provide data within the required response time, such a solution is difficult to provide. Such a scenario, together with the fact that the host-system processor cannot be externally interrupted during an operation, is why the cumbersome approach of the prior art appears to be the only possible solution.
It would be desirable to provide a memory-management system that is able to synchronously serve the demand of a host-system processor for code, providing the code wherever the code is stored (i.e. in the cache, in the RAM or in the NVM).